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VLSID
2004
IEEE
93views VLSI» more  VLSID 2004»
16 years 4 months ago
Random Access Scan: A solution to test power, test data volume and test time
Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara
DFT
2002
IEEE
117views VLSI» more  DFT 2002»
15 years 9 months ago
Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation
Conversion of the flip-flops of the circuit into scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthe...
Ozgur Sinanoglu, Alex Orailoglu
VTS
2005
IEEE
106views Hardware» more  VTS 2005»
15 years 9 months ago
Segmented Addressable Scan Architecture
This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consum...
Ahmad A. Al-Yamani, Erik Chmelar, Mikhail Grinchuc...
ISQED
2010
IEEE
121views Hardware» more  ISQED 2010»
15 years 9 months ago
A novel two-dimensional scan-control scheme for test-cost reduction
— This paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many l...
Chia-Yi Lin, Hung-Ming Chen
DATE
2006
IEEE
94views Hardware» more  DATE 2006»
15 years 10 months ago
Reuse-based test access and integrated test scheduling for network-on-chip
In this paper, we propose a new method for test access and test scheduling in NoC-based system. It relies on a progressive reuse of the network resources for transporting test dat...
Chunsheng Liu, Zach Link, Dhiraj K. Pradhan