Sciweavers

107 search results - page 5 / 22
» Re-Examining the Use of Network-on-Chip as Test Access Mecha...
Sort
View
BMCBI
2008
114views more  BMCBI 2008»
13 years 7 months ago
Testing the Coulomb/Accessible Surface Area solvent model for protein stability, ligand binding, and protein design
Background: Protein structure prediction and computational protein design require efficient yet sufficiently accurate descriptions of aqueous solvent. We continue to evaluate the ...
Marcel Schmidt am Busch, Anne Lopes, Najette Amara...
VTS
2003
IEEE
81views Hardware» more  VTS 2003»
14 years 22 days ago
Test Resource Partitioning and Optimization for SOC Designs
1 We propose a test resource partitioning and optimization technique for core-based designs. Our technique includes test set selection and test resource floor-planning with the ai...
Erik Larsson, Hideo Fujiwara
DAC
2003
ACM
14 years 8 months ago
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski,...
19
Voted
ATS
2003
IEEE
93views Hardware» more  ATS 2003»
14 years 23 days ago
Optimal System-on-Chip Test Scheduling
1 In this paper, we show that the scheduling of tests on the test access mechanism (TAM) is equivalent to independent job scheduling on identical machines and we make use of an exi...
Erik Larsson, Hideo Fujiwara
DATE
2006
IEEE
98views Hardware» more  DATE 2006»
14 years 1 months ago
Power-constrained test scheduling for multi-clock domain SoCs
This paper presents a wrapper and test access mechanism design for multi-clock domain SoCs that consists of cores with different clock frequencies during test. We also propose a t...
Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara