35 search results - page 4 / 7 » Scan Test Planning for Power Reduction |
ISQED
2010
IEEE
14 years 22 days ago
2010
IEEE
— This paper proposes a two-dimensional scan shift control concept for multiple scan chain design. Multiple scan chain test scheme provides very low scan power by skipping many l...
ITC
2003
IEEE
14 years 27 days ago
2003
IEEE
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
—X-filling is preferred for low-capture-power scan test generation, since it reduces IR-drop-induced yield loss without the need of any circuit modification. However, the effecti...
ATS
2004
IEEE
13 years 11 months ago
2004
IEEE
Conventional serial connection of internal scan chains brings the power and time penalty. A novel parallel core wrapper design (pCWD) approach is presented in this paper for reduc...
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consum...