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ICCAD
1998
IEEE
96views Hardware» more  ICCAD 1998»
14 years 2 months ago
Test set compaction algorithms for combinational circuits
This paper presents two new algorithms, Redundant Vector Elimination(RVE) and Essential Fault Reduction (EFR), for generating compact test sets for combinational circuits under th...
Ilker Hamzaoglu, Janak H. Patel
ASPDAC
2004
ACM
149views Hardware» more  ASPDAC 2004»
14 years 3 months ago
A coupling and crosstalk considered timing-driven global routing algorithm for high performance circuit design
With the exponential reduction in the scaling of feature size, inter-wire coupling capacitance becomes the dominant part of load capacitance. Two problems are introduced by coupli...
Jingyu Xu, Xianlong Hong, Tong Jing, Ling Zhang, J...
DAC
2003
ACM
14 years 11 months ago
Test cost reduction for SOCs using virtual TAMs and lagrange multipliers
Recent advances in tester technology have led to automatic test equipment (ATE) that can operate at up to several hundred MHz. However, system-on-chip (SOC) scan chains typically ...
Anuja Sehgal, Vikram Iyengar, Mark D. Krasniewski,...
HPCA
2005
IEEE
14 years 10 months ago
On the Limits of Leakage Power Reduction in Caches
If current technology scaling trends hold, leakage power dissipation will soon become the dominant source of power consumption in high performance processors. Caches, due to the f...
Yan Meng, Timothy Sherwood, Ryan Kastner
ICCAD
2002
IEEE
175views Hardware» more  ICCAD 2002»
14 years 6 months ago
Efficient model order reduction via multi-node moment matching
- The new concept of Multi-node Moment Matching (MMM) is introduced in this paper. The MMM technique simultaneously matches the moments at several nodes of a circuit using explicit...
Yehea I. Ismail