769 search results - page 33 / 154 » Timed Circuit Synthesis Using Implicit Methods |
DATE
2009
IEEE
14 years 5 months ago
2009
IEEE
— Clock-gating and power-gating have proven to be very effective solutions for reducing dynamic and static power, respectively. The two techniques may be coupled in such a way th...
ICCAD
1994
IEEE
14 years 2 months ago
1994
IEEE
A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a s...
ICCAD
1999
IEEE
14 years 2 months ago
1999
IEEE
Identifying repeating structural regularities in circuits allows the minimization of synthesis, optimization, and layout e orts. We introduce in this paper a novel method for ident...
VLSID
2002
IEEE
14 years 10 months ago
2002
IEEE
One of the major roadblocks in reduction of library generation cycle time is the layout generation phase. The two methods of doing automatic layout generation are synthesis and mig...
ASPDAC
2007
ACM
14 years 2 months ago
2007
ACM
In this paper, we present a method for generating checker circuits from sequential-extended regular expressions (SEREs). Such sequences form the core of increasingly-used Assertion...