639 search results - page 21 / 128 » Tradeoffs in designing accelerator architectures for visual ... |
DAC
2010
ACM
13 years 6 months ago
2010
ACM
Integrating a large number of on-chip voltage regulators holds the promise of solving many power delivery challenges through strong local load regulation and facilitates systemlev...
HPCA
2008
IEEE
14 years 3 months ago
2008
IEEE
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
IV
2007
IEEE
14 years 3 months ago
2007
IEEE
Research to date has demonstrated the apparent differences how architects, as ‘experts’ and members of the public as ‘non-experts’ perceive and understand visual represent...
DAC
1996
ACM
14 years 1 months ago
1996
ACM
This paper presents a methodology suited for high frequency analog IC design. The use of a top-down method with AHDL for circuit designers is proposed. In order to accelerate the ...
DAC
1996
ACM
14 years 1 months ago
1996
ACM
Superscalar processor developers are creatively leveraging best-in-class design verification tools to meet narrow market windows. Accelerated simulation is especially useful owing...