94 search results - page 13 / 19 » Wire width planning for interconnect performance optimizatio... |
GLVLSI
2009
IEEE
14 years 3 months ago
2009
IEEE
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split o...
DATE
2010
IEEE
13 years 7 months ago
2010
IEEE
Abstract—On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its to...
ICCAD
2001
IEEE
14 years 5 months ago
2001
IEEE
This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zero-skew clock meshes, with underlying zero-skew clock trees originating f...
ICCAD
1991
IEEE
13 years 12 months ago
1991
IEEE
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
ICCAD
2008
IEEE
14 years 5 months ago
2008
IEEE
Abstract— As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming increasing...