Sciweavers

NOCS
2010
IEEE
13 years 8 months ago
Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs
The number of cores present on-chip is increasing rapidly. The on-chip network that connects these cores needs to scale efficiently. The topology of on-chip networks is an importan...
Chia-Hsin Owen Chen, Niket Agarwal, Tushar Krishna...
ASPDAC
2010
ACM
143views Hardware» more  ASPDAC 2010»
13 years 9 months ago
A low latency wormhole router for asynchronous on-chip networks
Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than synchronous on-chip networks. A low latency asynchronous wormhole route...
Wei Song, Doug Edwards
ANCS
2005
ACM
14 years 4 months ago
Gigabit routing on a software-exposed tiled-microprocessor
This paper investigates the suitability of emerging tiled-architectures, equipped with low-latency on-chip networks, for high-performance network routing. In this paper, we presen...
Umar Saif, James W. Anderson, Anthony Degangi, Ana...
NOCS
2007
IEEE
14 years 5 months ago
On Characterizing Performance of the Cell Broadband Engine Element Interconnect Bus
Abstract – With the rise of multicore computing, the design of onchip networks (or networks on chip) has become an increasingly important component of computer architecture. The ...
Thomas William Ainsworth, Timothy Mark Pinkston
MICRO
2009
IEEE
99views Hardware» more  MICRO 2009»
14 years 5 months ago
Low-cost router microarchitecture for on-chip networks
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
John Kim
NOCS
2009
IEEE
14 years 5 months ago
Silicon-photonic clos networks for global on-chip communication
Future manycore processors will require energyefficient, high-throughput on-chip networks. Siliconphotonics is a promising new interconnect technology which offers lower power, h...
Ajay Joshi, Christopher Batten, Yong-Jin Kwon, Sco...
NOCS
2009
IEEE
14 years 5 months ago
Exploring concentration and channel slicing in on-chip network router
Sharing on-chip network resources efficiently is critical in the design of a cost-efficient network on-chip (NoC). Concentration has been proposed for on-chip networks but the t...
Prabhat Kumar, Yan Pan, John Kim, Gokhan Memik, Al...
GLVLSI
2009
IEEE
132views VLSI» more  GLVLSI 2009»
14 years 5 months ago
Multicast routing with dynamic packet fragmentation
Networks-on-Chip (NoCs) become a critical design factor as chip multiprocessors (CMPs) and systems on a chip (SoCs) scale up with technology. With fundamental benefits of high ban...
Young Hoon Kang, Jeff Sondeen, Jeffrey T. Draper
DAC
2001
ACM
14 years 12 months ago
Route Packets, Not Wires: On-Chip Interconnection Networks
Using on-chip interconnection networks in place of ad-hoc global wiring structures the top level wires on a chip and facilitates modular design. With this approach, system modules...
William J. Dally, Brian Towles