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ISCA
2011
IEEE
287views Hardware» more  ISCA 2011»
13 years 3 months ago
Scalable power control for many-core architectures running multi-threaded applications
Optimizing the performance of a multi-core microprocessor within a power budget has recently received a lot of attention. However, most existing solutions are centralized and cann...
Kai Ma, Xue Li, Ming Chen, Xiaorui Wang
ISCA
2011
IEEE
486views Hardware» more  ISCA 2011»
13 years 3 months ago
Dark silicon and the end of multicore scaling
Since 2005, processor designers have increased core counts to exploit Moore’s Law scaling, rather than focusing on single-core performance. The failure of Dennard scaling, to wh...
Hadi Esmaeilzadeh, Emily R. Blem, Renée St....
ISCA
2011
IEEE
386views Hardware» more  ISCA 2011»
13 years 3 months ago
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xi...
ISCA
2011
IEEE
240views Hardware» more  ISCA 2011»
13 years 3 months ago
Virtualizing performance asymmetric multi-core systems
Performance-asymmetric multi-cores consist of heterogeneous cores, which support the same ISA, but have different computing capabilities. To maximize the throughput of asymmetric...
Youngjin Kwon, Changdae Kim, Seungryoul Maeng, Jae...
ISCA
2011
IEEE
258views Hardware» more  ISCA 2011»
13 years 3 months ago
A case for heterogeneous on-chip interconnects for CMPs
Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the enti...
Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. ...
ISCA
2011
IEEE
229views Hardware» more  ISCA 2011»
13 years 3 months ago
TLSync: support for multiple fast barriers using on-chip transmission lines
As the number of cores on a single-chip grows, scalable barrier synchronization becomes increasingly difficult to implement. In software implementations, such as the tournament ba...
Jungju Oh, Milos Prvulovic, Alenka G. Zajic
ISCA
2011
IEEE
238views Hardware» more  ISCA 2011»
13 years 3 months ago
Rebound: scalable checkpointing for coherent shared memory
As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include ...
Rishi Agarwal, Pranav Garg, Josep Torrellas
ISCA
2011
IEEE
273views Hardware» more  ISCA 2011»
13 years 3 months ago
Bypass and insertion algorithms for exclusive last-level caches
Inclusive last-level caches (LLCs) waste precious silicon estate due to cross-level replication of cache blocks. As the industry moves toward cache hierarchies with larger inner l...
Jayesh Gaur, Mainak Chaudhuri, Sreenivas Subramone...
ISCA
2011
IEEE
294views Hardware» more  ISCA 2011»
13 years 3 months ago
Moguls: a model to explore the memory hierarchy for bandwidth improvements
In recent years, the increasing number of processor cores and limited increases in main memory bandwidth have led to the problem of the bandwidth wall, where memory bandwidth is b...
Guangyu Sun, Christopher J. Hughes, Changkyu Kim, ...
HPCA
2011
IEEE
13 years 3 months ago
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor
Queues are commonly used in multithreaded programs for synchronization and communication. However, because software queues tend to be too expensive to support finegrained paralle...
Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tu...