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ICCD
2007
IEEE
98views Hardware» more  ICCD 2007»
14 years 9 months ago
Evaluating voltage islands in CMPs under process variations
Parameter variations are a major factor causing powerperformance asymmetry in chip multiprocessors. In this paper, we analyze the effects of with-in-die (WID) process variations o...
Abhishek Das, Serkan Ozdemir, Gokhan Memik, Alok N...
ICCD
2007
IEEE
111views Hardware» more  ICCD 2007»
14 years 9 months ago
On modeling impact of sub-wavelength lithography on transistors
As the VLSI technology marches beyond 65 and 45nm process technologies, variation in gate length has a direct impact on leakage and performance of CMOS transistors. Due to sub-wav...
Aswin Sreedhar, Sandip Kundu
ICCD
2007
IEEE
200views Hardware» more  ICCD 2007»
14 years 9 months ago
A parallel IEEE P754 decimal floating-point multiplier
Decimal floating-point multiplication is important in many commercial applications including banking, tax calculation, currency conversion, and other financial areas. This paper...
Brian J. Hickmann, Andrew Krioukov, Michael J. Sch...
ICCD
2007
IEEE
179views Hardware» more  ICCD 2007»
14 years 9 months ago
Energy-aware co-processor selection for embedded processors on FPGAs
In this paper, we present co-processor selection problem for minimum energy consumption in hw/sw co-design on FPGAs with dual power mode. We provide theoretical analysis for the p...
Amir Hossein Gholamipour, Elaheh Bozorgzadeh, Suda...
ICCD
2007
IEEE
145views Hardware» more  ICCD 2007»
14 years 9 months ago
Effective Dynamic Thermal Management for MPEG-4 decoding
This paper proposes Dynamic Thermal Management (DTM) based on a dynamic voltage and frequency scaling (DVFS) technique for MPEG-4 decoding to guarantee thermal safety while mainta...
Inchoon Yeo, Heung Ki Lee, Eun Jung Kim, Ki Hwan Y...
ICCD
2007
IEEE
190views Hardware» more  ICCD 2007»
14 years 9 months ago
Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits
Hybrid nanoelectronics are emerging as one viable option to sustain the Moore’s Law after the CMOS scaling limit is reached. One main design challenge in hybrid nanoelectronics ...
Shu Li, Tong Zhang
ICCD
2007
IEEE
157views Hardware» more  ICCD 2007»
14 years 9 months ago
Limits on voltage scaling for caches utilizing fault tolerant techniques
This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume lit...
Mohammad A. Makhzan, Amin Khajeh Djahromi, Ahmed M...
ICCD
2007
IEEE
746views Hardware» more  ICCD 2007»
14 years 9 months ago
Hardware design of a Binary Integer Decimal-based floating-point adder
Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it are included in the IEEE Draft Standard for Floating-point Arithmetic (IEEE P75...
Charles Tsen, Sonia Gonzalez-Navarro, Michael J. S...
ICCD
2007
IEEE
146views Hardware» more  ICCD 2007»
14 years 9 months ago
Exploring DRAM cache architectures for CMP server platforms
As dual-core and quad-core processors arrive in the marketplace, the momentum behind CMP architectures continues to grow strong. As more and more cores/threads are placed on-die, ...
Li Zhao, Ravi R. Iyer, Ramesh Illikkal, Donald New...
ICCD
2007
IEEE
151views Hardware» more  ICCD 2007»
14 years 9 months ago
Benchmarks and performance analysis of decimal floating-point applications
The IEEE P754 Draft Standard for Floating-point Arithmetic provides specifications for Decimal Floating-Point (DFP) formats and operations. Based on this standard, many developer...
Liang-Kai Wang, Charles Tsen, Michael J. Schulte, ...