ICCD
2007
IEEE
14 years 9 months ago
2007
IEEE
As chip multiprocessors (CMPs) become the only viable way to scale up and utilize the abundant transistors made available in current microprocessors, the design of on-chip network...
ICCD
2007
IEEE
14 years 9 months ago
2007
IEEE
On-chip caches take a large portion of the chip area. They are much more vulnerable to parameter variation than smaller units. As leakage current becomes a significant component ...
ICCD
2007
IEEE
14 years 9 months ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
ICCD
2007
IEEE
14 years 9 months ago
2007
IEEE
This paper explores statistical simulation as a fast simulation technique for driving chip multiprocessor (CMP) design space exploration. The idea of statistical simulation is to ...
ICCD
2007
IEEE
14 years 9 months ago
2007
IEEE
Physical layout generation of RF embedded passive design is not an easy task since the response of a given layout is tightly coupled with the response of the individual components...
ICCD
2007
IEEE
14 years 9 months ago
2007
IEEE
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
ICCD
2007
IEEE
14 years 9 months ago
2007
IEEE
Fin-type field-effect transistors (FinFETs) are promising substitutes for bulk CMOS in nano-scale circuits. In this paper, it is observed that in spite of improved device charact...
ICCD
2007
IEEE
14 years 9 months ago
2007
IEEE
The cache hierarchy of state-of-the-art—especially multicore—microprocessors consumes a significant amount of area and energy. A significant amount of research has been devo...
ICCD
2007
IEEE
14 years 9 months ago
2007
IEEE
The deployment of future deep submicron technology calls for a careful review of existing cache organizations and design practices in terms of yield and performance. This paper pr...
ICCD
2007
IEEE
14 years 9 months ago
2007
IEEE
This paper presents the Finished Store Buffer (or FSB), an alternative and position-insensitive approach for building a scalable store buffer for an out-of-order processor. Exploi...