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ISQED
2007
IEEE
151views Hardware» more  ISQED 2007»
14 years 3 months ago
Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations
We propose gate level statistical simulation to bridge the gap between the most accurate Monte Carlo SPICE simulation and the most efficient circuit level statistical static timi...
Bao Liu
ISCAS
2007
IEEE
101views Hardware» more  ISCAS 2007»
14 years 3 months ago
Automated HDL Generation: Comparative Evaluation
— Reconfigurable computing (RC) systems, coupling general purpose processor with reconfigurable components, offer a lot of advantages. Nevertheless, currently a designer needs ...
Yana Yankova, Koen Bertels, Stamatis Vassiliadis, ...
ISCA
2007
IEEE
114views Hardware» more  ISCA 2007»
14 years 3 months ago
Matrix scheduler reloaded
From multiprocessor scale-up to cache sizes to the number of reorder-buffer entries, microarchitects wish to reap the benefits of more computing resources while staying within po...
Peter G. Sassone, Jeff Rupley, Edward Brekelbaum, ...
ISCA
2007
IEEE
149views Hardware» more  ISCA 2007»
14 years 3 months ago
An effective hybrid transactional memory system with strong isolation guarantees
We propose signature-accelerated transactional memory (SigTM), a hybrid TM system that reduces the overhead of software transactions. SigTM uses hardware signatures to track the r...
Chi Cao Minh, Martin Trautmann, JaeWoong Chung, Au...
ISCA
2007
IEEE
146views Hardware» more  ISCA 2007»
14 years 3 months ago
Virtual hierarchies to support server consolidation
Server consolidation is becoming an increasingly popular technique to manage and utilize systems. This paper develops CMP memory systems for server consolidation where most sharin...
Michael R. Marty, Mark D. Hill
ISCA
2007
IEEE
113views Hardware» more  ISCA 2007»
14 years 3 months ago
Thermal modeling and management of DRAM memory systems
With increasing speed and power density, high-performance memories, including FB-DIMM (Fully Buffered DIMM) and DDR2 DRAM, now begin to require dynamic thermal management (DTM) a...
Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard Da...
ISCA
2007
IEEE
126views Hardware» more  ISCA 2007»
14 years 3 months ago
Comparing memory systems for chip multiprocessors
There are two basic models for the on-chip memory in CMP systems: hardware-managed coherent caches and software-managed streaming memory. This paper performs a direct comparison o...
Jacob Leverich, Hideho Arakida, Alex Solomatnikov,...
ISCA
2007
IEEE
110views Hardware» more  ISCA 2007»
14 years 3 months ago
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Much like multi-storey buildings in densely packed metropolises, three-dimensional (3D) chip structures are envisioned as a viable solution to skyrocketing transistor densities an...
Jongman Kim, Chrysostomos Nicopoulos, Dongkook Par...
ISCA
2007
IEEE
106views Hardware» more  ISCA 2007»
14 years 3 months ago
Architectural implications of brick and mortar silicon manufacturing
We introduce a novel chip fabrication technique called “brick and mortar”, in which chips are made from small, pre-fabricated ASIC bricks and bonded in a designer-specified a...
Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, ...
ISCA
2007
IEEE
115views Hardware» more  ISCA 2007»
14 years 3 months ago
VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization
Indirect branches have become increasingly common in modular programs written in modern object-oriented languages and virtualmachine based runtime systems. Unfortunately, the pred...
Hyesoon Kim, José A. Joao, Onur Mutlu, Chan...