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ISQED
2007
IEEE
119views Hardware» more  ISQED 2007»
14 years 3 months ago
Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs
Abstract— Self-calibrating designs have recently gained momentum as an alternative to methods relying on worst-case characterisation of silicon [2], [4], [8]. So far, reliable op...
Frederic Worm, Patrick Thiran, Paolo Ienne
ISQED
2007
IEEE
165views Hardware» more  ISQED 2007»
14 years 3 months ago
On-Line Adjustable Buffering for Runtime Power Reduction
We present a novel technique to exploit the power-performance tradeoff. The technique can be used stand-alone or in conjunction with dynamic voltage scaling, the mainstream techn...
Andrew B. Kahng, Sherief Reda, Puneet Sharma
ISQED
2007
IEEE
372views Hardware» more  ISQED 2007»
14 years 3 months ago
From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit
Problems in computational finance share many of the characteristics that challenge us in statistical circuit analysis: high dimensionality, profound nonlinearity, stringent accura...
Amith Singhee, Rob A. Rutenbar
ISQED
2007
IEEE
206views Hardware» more  ISQED 2007»
14 years 3 months ago
Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations
Abstract—A Network-on-Chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected...
Mosin Mondal, Tamer Ragheb, Xiang Wu, Adnan Aziz, ...
ISQED
2007
IEEE
160views Hardware» more  ISQED 2007»
14 years 3 months ago
On-Chip Inductance in X Architecture Enabled Design
The inductance effects become significant for sub-100nm process designs due to increasing interconnect lengths, lower interconnect resistance values and fast signal transition tim...
Santosh Shah, Arani Sinha, Li Song, Narain D. Aror...
ISQED
2007
IEEE
127views Hardware» more  ISQED 2007»
14 years 3 months ago
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Ch...
ISQED
2007
IEEE
97views Hardware» more  ISQED 2007»
14 years 3 months ago
Probabilistic Congestion Prediction with Partial Blockages
— Fast and accurate routing congestion estimation is essential for optimizations such as floorplanning, placement, buffering, and physical synthesis that need to avoid routing c...
Zhuo Li, Charles J. Alpert, Stephen T. Quay, Sachi...
ISQED
2007
IEEE
120views Hardware» more  ISQED 2007»
14 years 3 months ago
Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-Architecture
With its advantages in wirelength reduction and routing flexibility compared with Manhattan routing, X-architecture has been proposed and applied to modern IC design. As a critic...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu, ...
ISQED
2007
IEEE
107views Hardware» more  ISQED 2007»
14 years 3 months ago
Recursive Function Smoothing of Half-Perimeter Wirelength for Analytical Placement
Inspired by recent success of analytical placers that use a logarithmsum-exponential (LSE) to smooth half-perimeter wirelength (HPWL), we consider in this paper two alternative sm...
Chen Li 0004, Cheng-Kok Koh
ISQED
2007
IEEE
135views Hardware» more  ISQED 2007»
14 years 3 months ago
Design of a Window Comparator with Adaptive Error Threshold for Online Testing Applications
Amit Laknaur, Rui Xiao, Sai Raghuram Durbha, Haibo...