DDECS
2007
IEEE
14 years 3 months ago
2007
IEEE
– The implementation and the fault simulation technique for the highly reliable digital design using two FPGAs under a processor control is presented. Two FPGAs are used for dupl...
DDECS
2007
IEEE
14 years 3 months ago
2007
IEEE
– This paper addresses an efficient concurrent fault detection scheme for the SBox hardware implementation of the AES algorithm. Concurrent fault detection is important not only ...
DDECS
2007
IEEE
14 years 3 months ago
2007
IEEE
This paper proposes debug patterns combined with an intuitive flow to accelerate and simplify the debugging of SystemC designs. A debug pattern provides a formalized procedure to f...
DDECS
2007
IEEE
14 years 3 months ago
2007
IEEE
– Algorithmic State Machines are a 40-year old tool for the design of digital circuits. They are a good alternative to Finite State Machines, where only states can be properly de...
DDECS
2007
IEEE
14 years 3 months ago
2007
IEEE
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
DDECS
2007
IEEE
14 years 3 months ago
2007
IEEE
Logic Soft Errors caused by radiation are a major concern when working with circuits that need to operate in harsh environments, such as space or avionics applications, where soft ...
DDECS
2007
IEEE
14 years 3 months ago
2007
IEEE
: In this paper we study Complex Read Faults in SRAMs, a combination of various malfunctions that affect the read operation in nanoscale memories. All the memory elements involved ...
DDECS
2007
IEEE
14 years 3 months ago
2007
IEEE
DDECS
2007
IEEE
14 years 3 months ago
2007
IEEE
— Recently, there is a renewed interest in Automatic Test Pattern Generation (ATPG) based on Boolean Satisfiability (SAT). This results from the availability of very powerful SA...
DATE
2007
IEEE
14 years 3 months ago
2007
IEEE