NPTest CMOS formatter, embedded within the new timing generation IC, can provide formatted levels and internal strobe markers for eight independent pinelectronics channels at up t...
– It is well known that the output signals measured by an automatic test equipment (ATE) system are not only due to the device-under-test (DUT), but also due to the test path. Fo...
Diagnosing failing vectors in a Built-In Self Test (BIST) environment is a difficult task because of the highly compressed signature coming out of the Multiple Input Shift Regist...
For ratio-Iddq testing, the test performance is significantly affected by the correlation between two currents of different input patterns as process parameters vary. In this p...
Composite microsystems that integrate mechanical and fluidic components are fast emerging as the next generation of system-on-chip designs. As these systems become widespread in s...
Abstract: We discuss the development of Built-In SelfTest (BIST) configurations that test all of the programmable logic and interconnect resources in the core of Xilinx 4000E, 4000...
Charles E. Stroud, Keshia N. Leach, Thomas A. Slau...
We present a novel methodology for concurrent error detection in linear analog circuits. We develop a rigorous theory that yields an error detection circuit of size that is, in ge...
Backside light emission and electrical measurements were used to evaluate the susceptibility to latchup of externally cabled I/O pins for a 0.13 µm technology generation [1,2] te...
Franco Stellari, Peilin Song, Moyra K. McManus, Ro...
This paper is a technology review of PXI. It describes the basic PXI architecture and looks in more detail at the features of the slot 2 timing and triggering module.