The DFT and Test challenges faced, and the solutions applied, to the ARM1026EJ microprocessor core are described in this paper. New DFT techniques have been created to address the...
Teresa L. McLaurin, Frank Frederick, Rich Slobodni...
— Being able to test the intrinsic performance of a device under test (DUT) has always been the main goal of a test engineer. Achieving this goal is becoming increasingly diffic...
Electrical testing of MicroElectroMechanical Systems (MEMS) can take on many different forms including wafer probing, electrical trimming, final test at temperatures, engineering ...
Theresa Maudie, Alex Hardt, Rick Nielsen, Dennis S...
This paper argues that the existing approaches to modeling and characterization of IC malfunctions are inadequate for test and yield learning of Deep Sub-Micron (DSM) products. Tr...
Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Tho...
A BIST method measures accumulated jitter over N periods and requires no external references. Simulation using a 0.25um process shows a 625MHz - 1GHz input range with resolution o...
Henry C. Lin, Karen Taylor, Alan Chong, Eddie Chan...
Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and do...
When developing new designs, debugging the prototype is important to resolve application malfunction. During this board design debug, often a few pins of an IC are measured to che...
Leon van de Logt, Frank van der Heyden, Tom Waayer...
A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of...
This paper proposes an architecture for implementing a self-checking 4-bit carry select adder that can be extended to any n-bit addition. The overhead is directly proportional to ...