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ITC
2003
IEEE
222views Hardware» more  ITC 2003»
14 years 4 months ago
Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random Simulation
Functional verification of complex designs largely relies on the use of simulation in conjunction high-level verification languages (HVL) and test-bench automation (TBA) tools. In...
Mahesh A. Iyer
ITC
2003
IEEE
114views Hardware» more  ITC 2003»
14 years 4 months ago
Test-Based Model Generation For Legacy Systems
We study the extension of applicability of system-level testing techniques to the construction of a consistent model of (legacy) systems under test, which are seen as black boxes....
Hardi Hungar, Tiziana Margaria, Bernhard Steffen
ITC
2003
IEEE
112views Hardware» more  ITC 2003»
14 years 4 months ago
Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault
Intermittent scan chain hold-time fault is discussed in this paper and a method to diagnose the faulty site in a scan chain is proposed as well. Unlike the previous scan chain dia...
Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-...
ITC
2003
IEEE
116views Hardware» more  ITC 2003»
14 years 4 months ago
Circular BIST testing the digital logic within a high speed Serdes
High Speed Serializer Deserializers (serdes) are traditionally tested using functional BIST. This paper presents an improved BIST for testing the digital part of a serdes using ci...
Graham Hetherington, Richard Simpson
ITC
2003
IEEE
93views Hardware» more  ITC 2003»
14 years 4 months ago
Hybrid Multisite Testing at Manufacturing
This paper deals with Hybrid multisite testing of VLSI chips by utilizing automatic test equipment (ATE) in connection with built-in self-test (BIST). The performance of a multisi...
Hamidreza Hashempour, Fred J. Meyer, Fabrizio Lomb...
ITC
2003
IEEE
135views Hardware» more  ITC 2003»
14 years 4 months ago
VDD Ramp Testing for RF Circuits
José Pineda de Gyvez, Guido Gronthoud, Rash...
ITC
2003
IEEE
120views Hardware» more  ITC 2003»
14 years 4 months ago
High Quality ATPG for Delay Defects
: The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture smalldistributed delay de...
Puneet Gupta, Michael S. Hsiao
ITC
2003
IEEE
108views Hardware» more  ITC 2003»
14 years 4 months ago
Backplane Test Bus Applications For IEEE STD 1149.1
Prior to the mid 1980s, the dominance of through-hole packaging of integrated circuits (ICs) provided easy access to nearly every pin of every chip on a printed circuit board. Pro...
Clayton Gibbs
ITC
2003
IEEE
147views Hardware» more  ITC 2003»
14 years 4 months ago
Data flow within an open architecture tester
An open architecture tester allows a third party to develop its own instrument. Such a tester must be open in the sense that it needs to be able to integrate this instrument with ...
Maurizio Gavardoni
ITC
2003
IEEE
92views Hardware» more  ITC 2003»
14 years 4 months ago
Infrastructure IP for Back-End Yield Improvement
The objective of this paper is to present an infrastructure IP (I-IP) designed to characterize yield loss in the process back-end. The I-IP structure is described in using a botto...
L. Forli, Jean Michel Portal, Didier Née, B...