As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
In this paper we present a centralized flow control scheme in NoCs in the presence of both elastic and streaming flow traffic paradigms. We model the desired Best Effort (BE) sour...
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Io...
This paper gives a correctness proof for the on-chip COMA cache coherence protocol that supports the Microgrid of microtheaded architecture, a multi-core architecture capable of in...
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...