276 search results - page 10 / 56 » Extremely Low-Power Logic |
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
This paper combines an adaptive supply-voltage scheme with self-timed CMOS digital design, to achieve low power performance. The supply-voltage automatically tracks the input data...
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
DAC
2004
ACM
14 years 1 months ago
2004
ACM
In order to improve the testabilities and power consumption, a new state assignment technique based on m-block partition is introduced in this paper. The length and number of feed...
JOLPE
2010
13 years 6 months ago
2010
This paper presents a low-power soft error-hardened latch suitable for reliable circuit operation. The proposed circuit uses redundant feedback loop to protect latch against soft e...