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ICCAD
2003
IEEE
123views Hardware» more  ICCAD 2003»
14 years 4 months ago
Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion
In this paper, we study the full-chp interconnect power modeling. ,We show that repeater,insertion is no longer sufficient to achievethe targetfrequencies specifiedhy ITRS, and de...
Weiping Liao, Lei He
DFT
2003
IEEE
145views VLSI» more  DFT 2003»
14 years 24 days ago
System-Level Analysis of Fault Effects in an Automotive Environment
In the last years, new requirements in terms of vehicle performance increased significantly the amount of on-board electronics, thus raising more concern about safety and fault to...
Fulvio Corno, S. Tosato, P. Gabrielli
HPCA
2008
IEEE
14 years 7 months ago
System level analysis of fast, per-core DVFS using on-chip switching regulators
Portable, embedded systems place ever-increasing demands on high-performance, low-power microprocessor design. Dynamic voltage and frequency scaling (DVFS) is a well-known techniq...
Wonyoung Kim, Meeta Sharma Gupta, Gu-Yeon Wei, Dav...
DATE
2007
IEEE
96views Hardware» more  DATE 2007»
14 years 1 months ago
Self-heating-aware optimal wire sizing under Elmore delay model
Global interconnect temperature keeps rising in the current and future technologies due to self-heating and the adiabatic property of top metal layers. The thermal e ects impact a...
Min Ni, Seda Ogrenci Memik
ISPD
1998
ACM
88views Hardware» more  ISPD 1998»
13 years 11 months ago
An efficient technique for device and interconnect optimization in deep submicron designs
In this paper, we formulate a new class of optimization problem, named the general CH-posynomial program, and reveal the general dominance property. We propose an efcient algorith...
Jason Cong, Lei He