491 search results - page 18 / 99 » Leakage power modeling and optimization in interconnection n... |
DAC
2002
ACM
14 years 9 months ago
2002
ACM
In this paper, we introduce a framework to estimate the power consumption on switch fabrics in network routers. We propose different modeling methodologies for node switches, inte...
IPPS
1998
IEEE
14 years 7 days ago
1998
IEEE
This paper shows the power of randomization in designing e cient parallel algorithms for the problems of routing and PRAM emulation. We show that with randomization techniques opti...
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
—Recent developments have shown the possibility of leveraging silicon nanophotonic technologies for chip-scale interconnection fabrics that deliver high bandwidth and power effi...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
The Y-architecture for on-chip interconnect is based on pervasive use of 0-, 120-, and 240-degree oriented semi-global and global wiring. Its use of three uniform directions explo...
ICCAD
1996
IEEE
14 years 5 days ago
1996
IEEE
In this paper, we study the simultaneous transistor and interconnect sizing (STIS) problem. We de ne a class of optimization problems as CH-posynomial programs and reveal a genera...