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TVLSI
2010
13 years 3 months ago
Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
Rupak Samanta, Jiang Hu, Peng Li
DAC
2011
ACM
12 years 8 months ago
Thermal-aware cell and through-silicon-via co-placement for 3D ICs
Existing thermal-aware 3D placement methods assume that the temperature of 3D ICs can be optimized by properly distributing the power dissipations, and ignoring the heat conductiv...
Jason Cong, Guojie Luo, Yiyu Shi
GLVLSI
2009
IEEE
125views VLSI» more  GLVLSI 2009»
14 years 3 months ago
Redundant wire insertion for yield improvement
Based on the insertion of internal and external redundant wires into L-type and U-type wires, an efficient two-phase reliability-driven insertion algorithm is proposed to insert r...
Jin-Tai Yan, Zhi-Wei Chen
TVLSI
1998
83views more  TVLSI 1998»
13 years 8 months ago
Low overhead fault-tolerant FPGA systems
— Fault-tolerance is an important system metric for many operating environments, from automotive to space exploration. The conventional technique for improving system reliability...
John Lach, William H. Mangione-Smith, Miodrag Potk...
DAC
2003
ACM
14 years 10 months ago
Temporofunctional crosstalk noise analysis
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal tra...
Donald Chai, Alex Kondratyev, Yajun Ran, Kenneth H...