97 search results - page 18 / 20 » SRAM Cell Current in Low Leakage Design |
DAC
2006
ACM
14 years 8 months ago
2006
ACM
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
VLSID
2006
IEEE
14 years 7 months ago
2006
IEEE
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
TVLSI
2010
13 years 1 months ago
2010
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise mar...
ISCA
2010
IEEE
13 years 11 months ago
2010
IEEE
As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-volatile resistive memories are being developed as a potential replacement. Unfortunat...
ASPDAC
2009
ACM
13 years 11 months ago
2009
ACM
— In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise pro...