Sciweavers

GLVLSI
2009
IEEE
167views VLSI» more  GLVLSI 2009»
14 years 6 months ago
Dual-threshold pass-transistor logic design
This paper introduces pass-transistor logic design with dualthreshold voltages. A set of single-rail, fully restored, passtransistor gates are presented. Logic transistors are imp...
Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. ...
GLVLSI
2009
IEEE
131views VLSI» more  GLVLSI 2009»
14 years 6 months ago
Octilinear redistributive routing in bump arrays
This paper proposes a scheme for automatic re-distribution layer (RDL) routing, which is used in chip-package connections. Traditional RDL routing designs are mostly performed man...
Renshen Wang, Chung-Kuan Cheng
GLVLSI
2009
IEEE
112views VLSI» more  GLVLSI 2009»
14 years 6 months ago
The effect of design parameters on single-event upset sensitivity of MOS current mode logic
In this paper, we describe and discuss the effects of design parameters such as transistor size, output voltage swing and bias current on radiation sensitivity of MOS current mode...
Mahta Haghi, Jeff Draper
GLVLSI
2009
IEEE
189views VLSI» more  GLVLSI 2009»
14 years 6 months ago
High-performance, cost-effective heterogeneous 3D FPGA architectures
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...
Roto Le, Sherief Reda, R. Iris Bahar
GLVLSI
2009
IEEE
104views VLSI» more  GLVLSI 2009»
14 years 6 months ago
Polynomial coefficient based DC testing of non-linear analog circuits
Suraj Sindia, Virendra Singh, Vishwani D. Agrawal
GLVLSI
2009
IEEE
150views VLSI» more  GLVLSI 2009»
14 years 6 months ago
Contradictory antecedent debugging in bounded model checking
In the context of formal verification Bounded Model Checking (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a...
Daniel Große, Robert Wille, Ulrich Kühn...
GLVLSI
2009
IEEE
154views VLSI» more  GLVLSI 2009»
14 years 6 months ago
Design of a maximum-likelihood detector for cooperative communications in intersymbol interference channels
Recently, cooperative communication has attracted a lot of attention for its potential to increase spatial diversity. However, limited attention has been paid to the physical laye...
Yanjie Peng, Andrew G. Klein, Xinming Huang
GLVLSI
2009
IEEE
125views VLSI» more  GLVLSI 2009»
14 years 6 months ago
Timing-driven N-way decomposition
Logic decomposition has been extensively used to optimize the worst-case delay and the area in the technology independent phase. Bi-decomposition is one of the state-of-art techni...
David Bañeres, Jordi Cortadella, Michael Ki...
GLVLSI
2009
IEEE
186views VLSI» more  GLVLSI 2009»
14 years 6 months ago
Bitmask-based control word compression for NISC architectures
Implementing a custom hardware is not always feasible due to cost and time considerations. No instruction set computer (NISC) architecture is one of the promising direction to des...
Chetan Murthy, Prabhat Mishra
GLVLSI
2009
IEEE
125views VLSI» more  GLVLSI 2009»
14 years 6 months ago
Redundant wire insertion for yield improvement
Based on the insertion of internal and external redundant wires into L-type and U-type wires, an efficient two-phase reliability-driven insertion algorithm is proposed to insert r...
Jin-Tai Yan, Zhi-Wei Chen