ASPDAC
2006
ACM
14 years 13 days ago
2006
ACM
ASPDAC
2006
ACM
14 years 13 days ago
2006
ACM
Abstract-- Shrinking process geometries and frequency scaling give rise to an increasing number of interconnects that require multiple clock cycles. This paper explores efficient t...
ASPDAC
2006
ACM
14 years 13 days ago
2006
ACM
The design of a large chip is typically hierarchical
ASAP
2006
IEEE
14 years 13 days ago
2006
IEEE
We present hereafter a framework for on-chip traffic generation and networks-on-chip performance evaluation. This framework is based on a traffic generator that has three importan...
ASAP
2006
IEEE
14 years 13 days ago
2006
IEEE
Early FPGA researchers understood that FPGAs made possible the creation of a new, flexible, and powerful class of machine -- the configurable computing machine (CCM). The earliest...
ASAP
2006
IEEE
14 years 13 days ago
2006
IEEE
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper pr...
ASAP
2006
IEEE
14 years 13 days ago
2006
IEEE
State-of-the-art communication standards make extensive use of Turbo codes. The complex and power consuming designs that currently implement the turbo decoder expose the need for ...
ASAP
2006
IEEE
14 years 13 days ago
2006
IEEE
A popular approach to guarantee fault tolerance in safety-critical applications is to run the application on two processors. A checkpoint is inserted at the completion of the prim...
ASAP
2006
IEEE
14 years 13 days ago
2006
IEEE
In this paper, we propose a reconfigurable hardware accelerator for fixed-point-matrix-vector-multiply/add operations, capable to work on dense and sparse matrices formats. The pr...
ASAP
2006
IEEE
14 years 13 days ago
2006
IEEE
Parameterized static affine nested loop programs can be automatically converted to input-output equivalent Kahn Process Network specifications. These networks turn out to be close...