We present an efficient algorithm for identification of two-line bridges in combinational CMOS logic that narrows down the two-line bridge candidates based on tester responses for...
Thomas J. Vogels, Wojciech Maly, R. D. (Shawn) Bla...
–This paper provides proof of concept for the newly-approved 1149.6 standard by investigating the first silicon implementation of the test receiver. EXTEST and EXTEST_PULSE tests...
NPTest CMOS formatter, embedded within the new timing generation IC, can provide formatted levels and internal strobe markers for eight independent pinelectronics channels at up t...
– It is well known that the output signals measured by an automatic test equipment (ATE) system are not only due to the device-under-test (DUT), but also due to the test path. Fo...
Diagnosing failing vectors in a Built-In Self Test (BIST) environment is a difficult task because of the highly compressed signature coming out of the Multiple Input Shift Regist...
For ratio-Iddq testing, the test performance is significantly affected by the correlation between two currents of different input patterns as process parameters vary. In this p...
Composite microsystems that integrate mechanical and fluidic components are fast emerging as the next generation of system-on-chip designs. As these systems become widespread in s...
Abstract: We discuss the development of Built-In SelfTest (BIST) configurations that test all of the programmable logic and interconnect resources in the core of Xilinx 4000E, 4000...
Charles E. Stroud, Keshia N. Leach, Thomas A. Slau...