Today’s ASIC designs consist of more memory in terms of both area and number of instances. The shrinking of geometries has an even greater effect upon memories due to their tigh...
Theo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Ome...
In a carefully structured study spanning several months, the authors visited numerous companies focused on Design For Test methodologies in SoC Test, Characterization, and Failure...
Knowing, that the threshold voltage of the EEPROM memory cells is a key parameter to determine the overall performance of the memory, a build in structure to extract this informat...
This paper discusses the adoption of Embedded Deterministic Test (EDT) at Infineon Technologies as a means to reduce the cost of manufacturing test without compromising test quali...
Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muh...
This paper describes a method for automatically generating diagnostic programs for mixed-signal load boards. This procedure employs a statistical method of computing Mahalanobis D...
Kranthi K. Pinjala, Bruce C. Kim, Pramodchandran N...
In this paper we analyze the effects of transient faults (TFs) affecting the internal nodes of conventional latch structures and we propose a new latch design which allows to tole...
: Empirical analyses of the IDDQ signatures of 0.18 µm devices indicate that IDDQ currents exhibit hysteresis. A newly proposed test method, SPIRIT (Single Pattern Iteration IDDQ ...
The long term impact of MEMS technology will be in its ability to integrate novel sensing and actuation functionality on traditional computing and communication devices enabling t...
We propose a procedure for designing an LFSRbased circuit for masking of unknown output values that appear in the output response of a circuit tested using LBIST. The procedure is...
Masao Naruse, Irith Pomeranz, Sudhakar M. Reddy, S...
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility ...