A technique to derive test vectors that exercise the worstcase delay effects in a domino circuit in the presence of crosstalk is described. A model for characterizing the delay of...
This paper proposes an architecture for implementing a self-checking 4-bit carry select adder that can be extended to any n-bit addition. The overhead is directly proportional to ...
Current-based tests are the most effective methods available to detect resistive shorts. Delta IDDQ testing is the most sensitive variant and can handle off-state currents of 10-1...
This paper describes a new post-silicon validation problem for diagnosing systematic timing errors. We illustrate the differences between timing validation and the traditional log...
Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M....
Creating functional tests that work on an ATE has always been a significant challenge [1]. This paper identifies the fundamental mechanisms for functional test failures of an SOC ...
Deliberate injection of faults into cryptographic devices is an effective cryptanalysis technique against symmetric and asymmetric encryption. We will describe a general concurren...
This paper describes an Addressable Shadow Protocol device that is capable of providing connectivity between a backplane resident IEEE 1149.1 test bus master and a plurality of 11...
Many of the semiconductor technologies are already facing limitations while new-generation data and telecommunication systems are implemented. Although in its infancy, superconduc...