As the performance of Analog-to-Digital Converters continues to improve, it is becoming more challenging and costly to develop sufficiently fast and low-drift signal generators th...
Le Jin, Kumar L. Parthasarathy, Turker Kuyel, Dega...
Energy Consumption Ratio (ECR) test, a current-based test, has shown its ability to reduce the impact of process variations and detect hard-to-detect faults. The effectiveness of ...
A delay-locked loop (DLL) based built-in self test (BIST) circuit has been designed with a 0.18 µ m TSMC process (CM018) to test chip I/O speeds, specifically, the setup and hold...
Functional verification of complex designs largely relies on the use of simulation in conjunction high-level verification languages (HVL) and test-bench automation (TBA) tools. In...
We study the extension of applicability of system-level testing techniques to the construction of a consistent model of (legacy) systems under test, which are seen as black boxes....
Intermittent scan chain hold-time fault is discussed in this paper and a method to diagnose the faulty site in a scan chain is proposed as well. Unlike the previous scan chain dia...
Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-...
High Speed Serializer Deserializers (serdes) are traditionally tested using functional BIST. This paper presents an improved BIST for testing the digital part of a serdes using ci...
This paper deals with Hybrid multisite testing of VLSI chips by utilizing automatic test equipment (ATE) in connection with built-in self-test (BIST). The performance of a multisi...
Hamidreza Hashempour, Fred J. Meyer, Fabrizio Lomb...
: The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture smalldistributed delay de...