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ITC
2003
IEEE
162views Hardware» more  ITC 2003»
14 years 4 months ago
FPGA Interconnect Delay Fault Testing
The interconnection network consumes the majority of die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple inter...
Erik Chmelar
ITC
2003
IEEE
176views Hardware» more  ITC 2003»
14 years 4 months ago
Instruction Based BIST for Board/System Level Test of External Memories and Internconnects
ct This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduc...
Olivier Caty, Ismet Bayraktaroglu, Amitava Majumda...
ITC
2003
IEEE
138views Hardware» more  ITC 2003»
14 years 4 months ago
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint
Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized...
Yannick Bonhomme, Patrick Girard, Loïs Guille...
ITC
2003
IEEE
177views Hardware» more  ITC 2003»
14 years 4 months ago
Analyzing the Effectiveness of Multiple-Detect Test Sets
Multiple-detect test sets have been shown to be effective in lowering defect level. Other researchers have noted that observing the effects of a defect can be controlled by sensit...
R. D. (Shawn) Blanton, Kumar N. Dwarakanath, Aniru...
ITC
2003
IEEE
170views Hardware» more  ITC 2003»
14 years 4 months ago
Double-Tree Scan: A Novel Low-Power Scan-Path Architecture
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zha...
ITC
2003
IEEE
126views Hardware» more  ITC 2003»
14 years 4 months ago
Impact of Multiple-Detect Test Patterns on Product Quality
This paper presents the impact of multiple-detect test patterns on outgoing product quality. It introduces an ATPG tool that generates multiple-detect test patterns while maximizi...
Brady Benware, Chris Schuermyer, Sreenevasan Ranga...
ITC
2003
IEEE
129views Hardware» more  ITC 2003»
14 years 4 months ago
Relating Yield Models to Burn-In Fall-Out in Time
An early-life reliability model is presented that allows wafer test information to be used to predict not only the total number of burn-in failures that occur for a given product,...
Thomas S. Barnett, Adit D. Singh
ITC
2003
IEEE
148views Hardware» more  ITC 2003»
14 years 4 months ago
HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk
As technology evolves into the deep sub-micron era, signal integrity problems are growing into a major challenge. An important source of signal integrity problems is the crosstalk...
Xiaoliang Bai, Sujit Dey, Angela Krstic
ITC
2003
IEEE
123views Hardware» more  ITC 2003»
14 years 4 months ago
Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores
1 This paper addresses the issue of testing and diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper that follows a progr...
Davide Appello, Paolo Bernardi, Alessandra Fudoli,...
ITC
2003
IEEE
151views Hardware» more  ITC 2003»
14 years 4 months ago
Fault Collapsing via Functional Dominance
A fault fj is said to dominate another fault fi if all tests for fi detect fj . When two faults dominate each other, they are called equivalent. Dominance and equivalence relation...
Vishwani D. Agrawal, A. V. S. S. Prasad, Madhusuda...