Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
With its advantages in wirelength reduction and routing flexibility compared with Manhattan routing, X-architecture has been proposed and applied to modern IC design. As a critic...
—In this paper the Cramér-Rao lower bound (CRLB) of an ultra-wideband (UWB) pulse amplitude modulated (PAM) signal with time hopping (TH) code is derived for the practical case ...
Modern systems-on-a-chip platforms support multiple clock domains, in which different sub-circuits are driven by different clock signals. Although the frequency of each domain can...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...
Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large cap...
Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Sha...
Clock meshes have found increasingly wide applications in today’s high-performance IC designs. The inherent routing redundancies associated with clock meshes lead to improved cl...
Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jia...
Abstract— Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous ap...
We present a distributed clock synchronization algorithm that guarantees an exponentially improved bound of O(log D) on the clock skew between neighboring nodes in any graph G of ...
Christoph Lenzen, Thomas Locher, Roger Wattenhofer
The current work describes a new standing wave oscillator scheme aimed for clock propagation on coplanar transmission lines on a silicon die. The design is aimed for clock signali...
In this paper we consider the model of communication where wireless devices can either switch their radios off to save energy (and hence, can neither send nor receive messages), o...