Previously-proposed strategies for VLSI fault diagnosis have su ered from a variety of self-imposed limitations. Some techniques are limited to a speci c fault model, and many wil...
David B. Lavo, Brian Chess, Tracy Larrabee, Ismed ...
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...
: In this paper a complete analysis of spot defects in industrial SRAMs will be presented. All possible defects are simulated, and the resulting electrical faults are transformed i...
This paper focuses on the development of a conceptual framework for integrating fault injection mechanisms into the RDD-100 tool2 to support the dependability analysis of computer...
: It has always been assumed that fault models in memories are sufficiently precise for specifying the faulty behavior. This means that, given a fault model, it should be possible...
— We present a probabilistic fault model that allows any number of gates in an integrated circuit to fail probabilistically. Tests for this fault model, determined using the theo...
Zhanglei Wang, Krishnendu Chakrabarty, Michael G&o...
Abstract: DRAMs play an important role in the semiconductor industry, due to their highly dense layout and their low price per bit. This paper presents the first framework of faul...
This paper summarizes advanced test patterns designed to target dynamic and time-related faults caused by new defect mechanisms in deep-submicron memory technologies. Such tests a...
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...
Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, ...