ICCAD
2003
IEEE
14 years 7 months ago
2003
IEEE
Process variations have become a critical issue in performance verification of high-performance designs. We present a new, statistical timing analysis method that accounts for int...
ASPDAC
2004
ACM
14 years 7 months ago
2004
ACM
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...
ISPD
2006
ACM
14 years 8 months ago
2006
ACM
Advanced process technologies call for a proactive consideration of process variations in design to ensure high parametric timing yield. Despite of its popular use in almost any h...
ISQED
2007
IEEE
14 years 8 months ago
2007
IEEE
Process related variations are considered a major concern in emerging sub-65nm technologies. In this paper, we investigate the impact of process variations on different types of c...
DATE
2007
IEEE
14 years 8 months ago
2007
IEEE
Deep-submicron designs have to take care of process variation effects as variations in critical process parameters result in large variations in access latencies of hardware compo...
VTS
2008
IEEE
14 years 8 months ago
2008
IEEE
With increasing IC process variation and increased operating speed, it is more likely that even subtle defects will lead to the malfunctioning of a circuit. Various fault models, ...
MICRO
2008
IEEE
14 years 8 months ago
2008
IEEE
—Negative bias temperature instability (NBTI), which reduces the lifetime of PMOS transistors, is becoming a growing reliability concern for sub-micrometer CMOS technologies. Par...
ISQED
2008
IEEE
14 years 8 months ago
2008
IEEE
In this paper we present a parasitic aware, process variation tolerant optimization methodology that may be applied to nanoscale circuits to ensure better yield. A currentstarved ...
DATE
2008
IEEE
14 years 8 months ago
2008
IEEE
In sub-90nm process technology it becomes harder to control the fabrication process, which in turn causes variations between the design-time parameters and the fabricated paramete...
MICRO
2009
IEEE
14 years 9 months ago
2009
IEEE
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...